Programmable logic devices which do not employ buffer registers are inherently asynchronous as viewed from external interface terminals. In order to make use of very low power (CMOS) devices, it is necessary that the internal circuitry structure of the programmable logic be synchronous.
One approach for providing synchronous operation has been to employ a chip enable control signal for both powering up the device prior to the matrix performing its logic function and for powering down the device after the matrix has finished performing its logic function. For programmable devices which employ bipolar transistors as the logic elements of the matrix, a forward bias is applied to the bipolar transistors in the power-down mode and, where appropriate, the devices are forward-biased in the power-up mode. Disadvantageously, however, the incorporation of a power transition cycle both prior to and subsequent to the operation of the matrix introduces a time delay which necessarily slows down the performance of the device.